1. Field of the Invention
The present invention relates to a semiconductor device and a method of testing the semiconductor device. In particular, the present invention relates to a method of testing a semiconductor device which has a plurality of memories using different data storage methods. This application is based upon and claims the benefit of priority from Japanese patent application No. 2007-028722 filed on Feb. 8, 2007, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of Related Art
With sophistication and enhancement of functionality of systems in recent years, MCP (Multi-Chip-Package) has been put into practical use. The MCP has a plurality of memories using different data storage methods (having different configurations) in the same package. Accordingly, memory capacity has continuously increased. It is necessary to conduct a test of checking functions of these memories prior to shipment. However, as capacity and kind of the memories included in the same package is increased more, a test time necessary for conducting the test becomes longer. As a result, test cost is increased, causing a problem that the semiconductor device cannot be provided at a low price. For this reason, there is a demand for a semiconductor device and a method of testing the semiconductor device which can reduce test time and test cost.
A first related art of reducing test time and test cost is disclosed in Japanese Laid-Open Patent Application JP-P 2001-067895 A (corresponding to U.S. Pat. No. 6,647,522 (B1)). In the first related art, as shown in FIG. 1 of JP-P 2001-067895 A, a semiconductor device (31) includes memory circuits (32, 33) having different structures, an operation control scan chain (34), signal control circuits (35, 36), failure determination circuits (37, 38) and an OR circuit (39) as a signal synthesis circuit, which are provided to perform an operation test of these memory circuits. These elements are formed in single chip. In the first related art, by providing one test pattern data to the memory circuits (32, 33) simultaneously and conducting operation tests of the memory circuits (32, 33), test time is reduced.
A second related art of reducing test time and test cost is disclosed in Japanese Laid-Open Patent Application JP-P 2002-304898 A. In the second related art, as shown in Figs. 2 and 4 of JP-P 2002-304898 A, after predetermined data is written into each memory cell of a SRAM chip, power source voltage VDDS of the SRAM chip is set to be lower than ordinary level, signal level of a chip enable signal #CE of the SRAM chip is set to a high level “H” to set the SRAM chip to standby state. In this data holding time, various tests of the flash chip are conducted, resulting in reduction of test time.
A third related art of reducing test time and test cost is disclosed in Japanese Laid-Open Patent Application JP-P 2003-346499 A (corresponding to U.S. Pat. No. 6,826,101 (B2) In the third related art, as shown in FIG. 1 (first embodiment), FIG. 2 (first test pattern) and FIG. 3 (flow chart of a data writing test in FIG. 1) of JP-P 2003-346499 A, in a semiconductor device including a flash ROM (40) and a logic circuit (30), the logic circuit (30) is tested in a writing period of the flash ROM (waiting time when a test pattern need not be inputted). The semiconductor device has a switching means of selecting either of an input path for test of the logic circuit (30) and an input path for test of the flash ROM (40) on the basis of a mode selection signal “mode” inputted from a control external terminal (53-2).
The third related art will be specifically described. First, a program is run (step S1 in FIG. 3 of JP-P 2003-346499 A) and a pattern input period T1 for writing into the flash ROM (40) passes (FIG. 2, a step S2 in FIG. 3 of JP-P 2003-346499 A). At this time, according to the mode selection signal “mode”, selectors (62-11, 62-12, 62-21, . . . ) are switched to the side of the logic circuit (30) and a test data path from external terminals (51-1, 51-2, . . . ) is switched from the side of the flash ROM (40) to the side of the logic circuit (30) (a step S3 in FIG. 3 of JP-P 2003-346499 A). Since the flash ROM (40) is in a wait state in the writing period T2 (200 μs) (FIG. 2 and step S4 in FIG. 3 of JP-P 2003-346499 A), during a logic pattern input period T3 which is equal to the writing period T2, a logic test pattern for testing the logic circuit (30) is inputted into the external terminals (51-1, 51-2, . . . ) at for 200 μs or less (FIG. 2 and a step S5 in FIG. 3 of JP-P 2003-346499 A). The logic test pattern inputted at the step S5 is sent to the logic circuit (30) through selectors (61-11, 61-12, 62-11, 62-1, 63-11, 63-12, . . . ). Then, a test operation is conducted at the logic circuit (30) and the test result is outputted from the external terminals (52-1, . . . ) through selectors (63-31, 62-21, 61-31, . . . ). The test result is tested by a tester to check whether or not the logic circuit (30) normally operates. Meanwhile, in the writing period T2 of the flash ROM (40), a memory test pattern of a first word is written into a memory cell for one word. When the time of 200 μs and the writing period T2 have passed, according to the mode selection signal “mode”, selectors (62-11, 62-12, 62-21, . . . ) are switched to the side of the flash ROM (40) and a test data path is switched from the side of the logic circuit (30) to the side of the flash ROM (40) (step S6 in FIG. 3 of JP-P 2003-346499 A). It is determined whether or not writing of all bits to the flash ROM (40) is finished. In this case, since only one word is written (No at a step S7 in FIG. 3 of JP-P 2003-346499 A), the procedure returns to the step S2 and a memory test pattern of a second word is written into a memory cell for the second word in the flash ROM (40) in the above-mentioned manner. When the above-mentioned processing is repeated by the number of memory cells of the flash ROM (40) and all bits of memory test pattern are finished, execution of the program is terminated (YES at the step S7 in FIG. 3 and S8 of JP-P 2003-346499 A). When execution of the program is terminated, all bits of data are output from the external terminals (52-1, . . . ) through selectors (63-41, 62-21, 61-31, . . . ). The read data is tested by a tester to check whether or not the flash ROM normally operates.
A fourth related art which relates to the technique of reducing test time and test cost is disclosed in Japanese Laid-Open Patent Application JP-A-Heisei 07-013954. In the fourth related art, as shown in FIG. 1 of JP-A-Heisei 07-013954, a microcomputer has an EEPROM (12) and a CPU (11) for controlling the whole of the microcomputer including the EEPROM (12) by a program. The microcomputer has a screening dedication test circuit (16) and a screening count register. The screening dedication test circuit (16) performs screening by writing and erasing data with respect to all or part of a storage area of the EEPROM (12), irrespective of a test conducted under control of the CPU (11) which is unrelated to the REPROM (12). At this time, the screening dedication test circuit (16) counts the number of times of screening on the basis of at least either of data writing or data erasure. The screening count register is formed of the EEPROM or another EEPROM and stores the count of the screening dedication test circuit (16) therein.
We have now discovered that the related arts have the following problems.
According to the first related art, one test pattern is supplied to a plurality of memory circuits simultaneously. For this reason, the first related art can be applied to a case where the plurality of memory circuits is the same memory type such as a RAM. However, there is a problem that memories using different data storage methods such as a RAM and a flash memory cannot be simultaneously tested due to difference between test conditions such as contents and speed.
The second related art fails to specifically describe the way to control the flash chip for conducting the test at the same time in the data holding period. For example, in a case where a memory capacity or the number of IO terminals of the SRAM chip is different from that of the flash memory chip, a method of controlling each of address terminals and IO terminals of the SRAM chip and the flash memory chip is unclear. Furthermore, according to the second related art, since the flash chip is tested in a state where a power source voltage VDDS of the SRAM chip is lowered, when power is supplied to the SRAM chip and the flash memory chip from the same power source, the SRAM chip and the flash memory chip cannot be tested at the same time.
According to the third related art, by conducting a test of another circuit (the logic circuit (30)) in the writing period of the flash ROM (40), test time is reduced. However, since the test of the another circuit is conducted by the unit of writing period for one word of the flash ROM (40), there is a problem that test having a long test time cannot be simultaneously conducted. That is, one attempts to apply the third related art to the flash ROM (40) and a DRAM and conduct a DRAM data holding test in the writing period of the flash ROM (40), the writing period for one word of the flash ROM (40) is generally a few μs to a few hundred of μs, while the DRAM data holding test generally requires test time of a few hundred of ms. Accordingly, in the third related art, contents of test that can simultaneously test the flash ROM (40) are limited and thus, the effect of reducing test time cannot be obtained. In addition, writing period of the flash ROM (40) is set to be longer than necessary to conduct the tests simultaneously, the specification of the writing period cannot be disadvantageously ensured.